| Time | Title | Presenter(s) | Main Topic |
|---|---|---|---|
| 08:30 - 10:00 | European Chiplet Innovation – APECS Pilot Line | P. Höhmann et al. (FMD) | Packaging / Systems |
| 10:00 - 10:30 | Coffee break | ||
| 10:30 - 12:00 | Analog IC Layout (AICL) Co-Pilot | M. Bio (FH Kärnten / JKU) | EDA / Automation |
| 12:00 - 13:00 | Lunch | ||
| 13:00 - 14:30 | Multi-Stacked More-than-Moore Emerging Devices | S. Dasgupta, N. Bagga (IIT) | Devices / Technology |
| 14:30 - 16:00 | Reliable Framework for Accurate Timing Sign-Off | A. Bulusu (IIT Roorkee) | Digital / EDA |
| 16:00 - 16:30 | Coffee Break | ||
| 16:30 - 18:00 | Optimal Equalizer Design for High-Speed Interfaces | J. Kim (SNU) | Mixed-Signal Systems |
| 18:00 - 20:00 | Welcome Reception | ||
| Time | Large Room | Session Room | |
|---|---|---|---|
| 08:30 - 09:00 | Opening | ||
| 09:00 - 10:00 | Plenary talk #1: | ||
| 10:00 - 10:40 | Coffee break/ POSTER SESSION | ||
| 3233 Félix David Suárez Bonilla, Gustavo Liñán-Cembrano and Jose M. de la Rosa. Hardware-Efficient Neural Architecture Search for Wireless Signal Classification on Edge Devices | |||
| 5773 Muhammad Waleed Hasan, Uwe Hatnik and Benjamin Prautsch. Performance of Ensemble Learning Algorithms for HCI Degradation Modeling of Planar MOSFETS | |||
| 4786 Matthias Thiele and Jens Lienig. Paving the Path to Spatially Multiplexed Coherent Ising Machines | |||
| 6558 Mohanlal Naik, Vaishali Choudhary and Pydi Ganga Bahubalindruni. A Linear Active Resistance Based Low-Voltage Low-pass Filter Using Oxide TFT Technology | |||
| 5812 Neha Gupta, Akash Shekhar, Lomash Chandra Acharya, Ajoy Mandal, Sudeb Dasgupta and Anand Bulusu. Prediction of Read Access Time for 6T SRAM for Bitcell Characterization and Sizing | |||
| 459 Miguel Martín-González, F. Eugenio Potestad-Ordóñez, Antonio J. Acosta and Erica Tena-Sánchez. A Composable Hybrid Boolean Masked and Internal Fault Injection-Detecting AND Gate Gadget Proposal | |||
| 10:40 | Physics-Based Reliability and Failure Analysis in Advanced Semiconductor Devices and Space-Grade Systems | Emerging Hardware Architectures for Quantum Readout, Synchronization, and Photonic Processing | |
| 10:40 | 3368 Susann Rothe, Jens Lienig and Sachin Sapatnekar. Fast Hotspot Analysis Applying Physics-based Electromigration Models | 3629 Gabriel López-Pinar, Concepción Aldea, Santiago Celma and Carlos Sánchez-Azqueta. A Fully Integrated CMOS Parametric Amplifier for Cryogenic Qubit Readout | |
| 11:00 | 8189 Javier Diaz-Fortuny, Francisco V. Fernandez, Javier Martin-Martinez, Montserrat Nafria, Elisenda Roca and Rafael Castro-Lopez. Characterizing Fast RTN Events with Parameter-Limited Instrumentation | 7566 Ashwin Raj Ravichandran, Bhuvnesh Narayanan, Christoph Posenau, Lorenz Reuschel and Michael Faulwaßer. Electro-Optic Modulator Control of Multi-Mode Photonic Processing Units for Optical Quantum Computing | |
| 11:20 | 9951 Nour El I Boukortt and Dirk Stroobandt. Design and Electrothermal Insights for 3D CFETs | 1927 Roque Fernandez-Maldonado, Uxua Esteban-Eraso, Concepcion Aldea, Santiago Celma and Carlos Sanchez-Azqueta. A Fractional-N PLL Frequency Synthesizer for Qubit Readout and Control Architectures | |
| 11:40 | 6824 Seyedmohammadhossein Sajjadikaboudi, Giorgio Cora, Corrado De Sio, Sarah Azimi and Luca Sterpone. Reliability Analysis of Optical Fiber Communication for FPGA Clusters in Space | 4853 Salwa Yasmeen Neyaz, Arun Ashok, Michael Schiek, Christian Grewing, Andre Zambanini, Sabitha Kusuma and Stefan van Waasen. A 28 nm PLL-Based Oscillator Network for Synchronization and Oscillator-based Optimization | |
| 12:00 - 13:20 | Lunch | ||
| 13:30 | Hardware Security Frontiers: IC Reuse Detection, TRNG Innovation, and Side-Channel Defense | Power Management and Energy Conversion | |
| 13:30 | 6960. Pablo Quintero-Viejo, Javier Diaz-Fortuny, Elisenda Roca, Francisco V. Fernandez and Rafael Castro-Lopez. Detecting IC Reuse via Reflow-Exposure Fingerprints in Pre-Stressed Ring Oscillators | 9305 Oran Hayes, Maria Pantazi, Athanasios Tziouvaras, George Stamoulis, Anuj Pathania, Shreejith Shanker and George Floros. Workload-Aware Early-Stage Power Delivery Network Optimization via Architectural Power Traces | |
| 13:50 | 3225 Larissa Andrade, Raphael Viera, Jean-Baptiste Rigaud, Laurent Le Brizoual, Laurent Pichon, Murilo Muller and Gevorg Ishkhanyan. On-Chip Frequency-to-Voltage Conversion for Hardware Security Characterization | 6067 Giulia Di Capua and Nicola Femia. Duty-Cycle Saturation Effects in Power Converters for Wireless Battery Charging Systems | |
| 14:10 | 4687 Bruno Fernández Sánchez-Hermosilla, Rafael Castro López, Elisenda Roca Moreno and Francisco V. Fernández. An Improved RTN-Based True Random Number Generation Technique Employing XOR Whitening | 2177 Eashan Wadhwa, Georgios Floros and Shreejith Shanker. Context-aware Simopt-Power: Using structural data with simulation metadata to optimise FPGA designs | |
| 14:30 | 953 Prashee Arora and Mitra Mirhassani Pre-Silicon Side-Channel Leakage Detection and Localization in ECC-Based ECDH Hardware | 618 Duarte Marques, Margarida Lourenço, Ricardo Martins and Fábio Passos. A Methodology-Driven Fully Integrated EMLC DC-DC Converter with Optimized Passives, Regulation and Reliability | |
| 14:50 - 15:20 | Coffee break | ||
| 15:20 | EDA Competition I | Innovations in Time-Measurement Circuits, Analog Signal Conditioning, and High-Frequency Design | |
| 15:20 | EDA Competition Presentation | 9841 Anıl Karaca and Mustafa Berke Yelten. Comparative Analysis of GaAs pHEMT VCO Types | |
| 15:30 - 16:00 | 6520 Veeti Lahtinen, Altti Heikkinen, Verneri Hirvonen, Aleksi Tamminen and Marko Kosunen. On Re-Usability and Process-Portability of Programmatic Mixed-Mode Integrated Circuit Design | ||
| 15:40 | 5768 Burak Kaya, Wolfgang Gläser, Thomas Thönes, Johan Berthier Tsayem and Heinrich Milosiu. Low-Power RF Circuit Design and Optimization with Fitted ACM2 MOSFET Models | ||
| 16:00 | 1391 Muhammet Enes Yanık, Abdullah Bayram, Ihsan Cicek and Engin Afacan. MARGO:Multi-Agent RTL-to-GDSII Orchestration | 6195 Jan-Philipp Gaa and Eckhard Hennig. An Interleaving Concept for Resolution Enhancement of Multi-Hit Time-to-Digital Converters for Time-of-Flight Sensor Applications | |
| 16:20 - 16:40 | 9003 Alex Bary, Arthur Perodou, Anton Korniienko, Pierre Courouve, Dominique Morche and Gérard Scorletti. Sizing of a weakly nonlinear Gm-C Filter based on sEKV model using Geometric Programming | ||
| 16:30 - 17:00 | 7548 Vaisakh Naduvodi Viswambharan and Ayush Dileep. SaxoFlow: An Agentic AI Platform for Hardware Design Research and Education | ||
| 19:00 - 21:00 | Gala Dinner | ||
| Time | Large Room | Session Room | |
|---|---|---|---|
| 09:00 - 10:00 | Plenary talk #2: | ||
| 10:00 | Coffee break/ POSTER SESSION | ||
| 3233 Félix David Suárez Bonilla, Gustavo Liñán-Cembrano and Jose M. de la Rosa. Hardware-Efficient Neural Architecture Search for Wireless Signal Classification on Edge Devices | |||
| 5773 Muhammad Waleed Hasan, Uwe Hatnik and Benjamin Prautsch. Performance of Ensemble Learning Algorithms for HCI Degradation Modeling of Planar MOSFETS | |||
| 4786 Matthias Thiele and Jens Lienig. Paving the Path to Spatially Multiplexed Coherent Ising Machines | |||
| 6558 Mohanlal Naik, Vaishali Choudhary and Pydi Ganga Bahubalindruni. A Linear Active Resistance Based Low-Voltage Low-pass Filter Using Oxide TFT Technology | |||
| 5812 Neha Gupta, Akash Shekhar, Lomash Chandra Acharya, Ajoy Mandal, Sudeb Dasgupta and Anand Bulusu. Prediction of Read Access Time for 6T SRAM for Bitcell Characterization and Sizing | |||
| 459 Miguel Martín-González, F. Eugenio Potestad-Ordóñez, Antonio J. Acosta and Erica Tena-Sánchez. A Composable Hybrid Boolean Masked and Internal Fault Injection-Detecting AND Gate Gadget Proposal | |||
| 10:40 | Layout Aware IC Design Automation and Post-Layout Performance Modeling | Advanced Data Converter and Sampling Circuit Design for High-Speed, High-Resolution, and Precision Sensing Applications | |
| 10:40 | 9906 Carlos Almeida, Filipe Azevedo, Marco Oliveira and Ricardo Martins -. Combining Layer-Aware Images and Pre-Layout Fusion for Accurate Analog IC Post-Layout Performance Prediction | 9478 Hakan Cetinkaya, Tufan Coşkun Karalar and Alper Girgin. A 3-b 1.6 GS/s Fully Differential Back-end Flash ADC in IHP SiGe 0.13 µm | |
| 11:00 | 3937 Hoang Nguyen, Trung Duong, Ricardo Martins and Lihong Zhang. RF Post-Layout Performance Prediction with Deep Learning and Image Processing | 7916 Kerem Yurtseven, Uygar Yildiz, Kemal Ozanoglu and Günhan Dündar. A Direct-Digitization Sigma-Delta ADC for Ionization Chamber Readout with fA-Level Sensitivity | |
| 11:20 | 4890 Behdad Jamadi, Farzad Ordubadi, Asif Wahid and Armin Tajalli. Automation Design flow of Analog Circuits | 8608 Ko-Chi Kuo and Juin Hung Ye. Adaptable 8-Bit Resolution SAR ADC for Analog CIM Applications | |
| 11:40 | 8520 Uwe Eichler, Torsten Reich, Uwe Hatnik and Benjamin Prautsch. Interactive Design of Optimized Capacitance Arrays using Intelligent IP Layout Generators | 4829 Mohammad Bayazi, Jiayi He and Renato Negra. A bootstrapped switch with enhanced rising speed and low distortion sampling structure | |
| 12:00 - 13:20 | Lunch | ||
| 13:30 | Circuit Verification and Model Order Reduction | AI-Driven and High-Frequency Circuit Design for Next-Generation Wireless Systems | |
| 13:30 | 8164 Jeonghoon Min, Ashwin Bhat, Adou Sangbone Assoa, Seoyeong Jo, Jaeha Kim and Sigang Ryu. XEDGE-SIM: Fast NPU-Level Simulator Unifying RRAM-Based CIM and Firmware-Aware Digital Subsystems for Mixed-Signal Verification | 1219 Islam Guven, Mehmet Parlak and Dimitri Lederer Hybrid Evolutionary–Reinforcement Learning Synthesis of Wideband D-Band Three-Port Circuits | |
| 13:50 | 1687 Christos Giamouzis, Dimitrios Garyfallou and Nestor Evmorfopoulos. Second-Order Balanced Truncation of RLCk Models via Frequency-Aware Rational Krylov Approximation | 8703 Francisco Aznar, Uxua Esteban Eraso, Guillermo Diez-Senorans, Danilo Tardioli and Santiago Celma PVT Analysis of Quadruple CMOS RX Front-End for Linear Phased Arrays | |
| 14:10 | 418 Caroline Draudt, Yasmine Abu-Haeyeh and Lars Hedrich. Modeling of Nonlinear Analog Circuits Using Automated Reachset Conformance Checking | 8976 Muhammed Taha Karaaslan, Alperen Tunç, Revna Acar Vural and Mustafa Berke Yelten Comparative Analysis of Resource-Constrained MPLS and Neural Network DPD in Deep Saturation | |
| 14:30 | 7402 Chrysostomos Chatzigeorgiou, Pavlos Stoikos, Dimitrios Chatzigeorgiou, Evangelos Nonas, Dimitrios Garyfallou, Nestor Evmorfopoulos and George Stamoulis. Optimal Reduction of Large-Scale Circuit Models by Tangential Interpolation | 5699 Manimohan Thiriloganathan, Shenal Ranasinghe, Avishka Herath, Rajinthan Rameshkumar, Hansa Marasinghe, Anjana Viduranga, Gayangana Leelarathne and Kithmin Wickremasinghe. A 2.4 GHz LC-VCO Fractional-N Phase Locked Loop Open-Source Design in 130-nm BiCMOS | |
| 14:50 - 15:10 | Coffee break | ||
| 15:10 | EDA Competition II | Electromagnetic Modeling and Integrated Passive Systems | |
| 15:20 | 7389 Utku Arda Akinci, Faik Baskaya and Gunhan Dundar. Continuous-Time Bandpass Filter Design, Modeling & Analysis Tool on MATLAB | 501 Giulia Di Capua, Nicola Femia, Gennaro Di Mambro and Antonio Maffucci. Data-Driven Behavioral Modeling of Mutual and Self-Inductance in Wireless Power Transfer Coils | |
| 15:40 | 7763 Marlene Schneider, Fikret Eren, David Brunner, Marcel Baunach, Bernd Deutschmann and Norbert Druml. Parametric Analysis and Optimization of the Start-up Process for 2D MEMS Mirrors | ||
| 15:50 | 629 Adrian Pitterling, Manuel Jirsak, Eric Schäfer and Georg Gläser. To Clock or Not to Clock: Clock Gating Using Netlist Carpentry | ||
| 16:00 | 2752 Sabina Pache-Viles, Gabriel Lopez-Pinar, Concepcion Aldea, Santiago Celma and Carlos Sanchez-Azqueta. On-Chip Stacked Transformer in a Low-Noise Amplifier for Cryogenic Environments | ||
| 16:20 - 16:40 | 3162 Erol Tunahan Gedik, Macit Uluda, Ali Emir Oktem, Gunhan Dundar and Arda Deniz Yalcinkaya. Monolithic Co-Integration of an Optically Powered 64 MHz Receiver with On-Chip Charge Pump | ||
| 16:20 - 16:50 | 5503 Matthew Bio, Santiago Sondon, Johannes Sturm and Harald Pretl. AICL Co-pilot: A Hybrid Framework for Hierarchical Analog IC Layout Automation | ||
| Time | Large Room | Session Room |
|---|---|---|
| 09:00 | Plenary talk/ tutorial #3: | |
| 10:00 | Coffee break | |
| 10:40 | Generative and Reinforcement Learning Methods for Scalable Analog Integrated Circuit Design and Optimization | Energy Harvesting and Self-Powered Systems |
| 10:40 | 4108 Filipe Azevedo, Duarte Marques, Carlos Almeida, Fábio Passos and Ricardo Martins. Generative Analog Integrated Circuit Placement via Denoising Diffusion Models | 2360 Mina Nazarian Samani, Sima A. Alidokht, Heloise Therien-Aubin and Lihong Zhang. A Bio-Inspired Starfish TENG Architecture for Ocean Wave Energy Harvesting: Modeling, Design, and Experimental Validation |
| 11:00 | 2510 Hakan Taskiran and Engin Afacan. Generative Design of Analog Circuits Under Limited Data via cVAE Manifold Modeling | 6141 Ali Namdari and Daniele D. Caviglia. A 79% Efficient Piezoelectric Harvester with Hybrid Hysteretic Control for Self-Powered Biomedical Sensor Nodes |
| 11:20 | 1328 Douglas Mateus Machado, Nathan Chanez, Severin Trochut, Paul Chollet, Roberto Guizzetti, Pascal Urard and Van-Tam Nguyen. Scalable Reinforcement Learning for Industrial Analog Circuit Sizing: A Curriculum Learning Approach | 9487 Abel Mwepu Tshimbu, Ting Zou and Lihong Zhang. Internal Impedance Prediction for Triboelectric Nanogenerators Using Artificial Neural Networks |
| 11:40 | 5095 Han Liu, Filipe Azevedo, Carlos Almeida, Hakan Taşkiran, Engin Afacan, Li Jiao and Ricardo Martins. Using Variational Autoencoders to Address the Inverse Sizing Design Problem of Analog Ics | 1820 Ali Namdari and Daniele D. Caviglia. A Sub-2-nW, 69-dB Gain Inverter-Based OTA for Energy-Harvesting Biomedical Sensor Nodes |
| 12:00 - 13:20 | Lunch | |
| 13:30 | AI-Assisted Methods for Sample-Efficient RF and Analog Circuit Design Automation | Memristive Devices and Energy-Aware Learning for Emerging Computing Systems |
| 13:30 | 2901 Islam Guven, Mehmet Parlak and Dimitri Lederer. World Model-Based Reinforcement Learning for Sample-Efficient Wideband Pixelated Passive RF Circuit Synthesis | 3560 Khang Phuoc Nguyen, Richard Schroedter, Vasileios Ntinas, Emilio Perez-Bosch Quesada, Eduardo Perez, Christian Wenger and Ronald Tetzlaff. A Variability-Aware Compact Memristor Model for HfO2-based 1T1R ReRAM Devices |
| 13:50 | 3743 Ali Al-Zawqari, Ali Safa, Dries Peumans and Gerd Vandersteen. Local Reranking for Retrieval-based Heterogeneous Analog/RF Design | 5267 Neethu Kuriakose, Arun Ashok, Sabitha Kusuma, Kay Winterberg, Christian Roth, Christian Grewing, Andre Zambanini and Stefan van Waasen. Memristor Conductance Control System-on-Chip Using Current Controlled Techniques in 28 nm CMOS Technology |
| 14:10 | 3619 Enes Sağlıcan, Kemal Ozanoglu, Günhan Dündar and Engin Afacan. LLMs on the Path Toward Analog IC Automation: ChatGPT as an ADC Design Expert | 1631 Hiba Al Youssef, Mohamad Raad, Maurizio Valle and Ali Ibrahim. EVA-NAS: Energy Variance Aware Neural Architecture Search for Resource Constrained Embedded Systems |
| 14:30 | Coffee break | |
| 15:00 | Next-Generation Design Automation for Complex Systems: AI, Physics-based, and Design Frameworks | Physics-Informed and Data-Driven Compact Modeling of Advanced Semiconductor Devices |
| 15:00 | 9012 Shangyu Wang, Shaoping Wang, Yaohui Lu and Jose de la Rosa. PRED: Probabilistic Routing Expert Diffusion for High-Level Design of Sigma-Delta Modulators | 129 Siddharth Mohan, Mike Engelhardt, Tim McCune and Jeff Strang. Datasheet‑Driven Automated Device Modeling |
| 15:20 | 7464 Thinh Do, Lihong Zhang, Trang Hoang and Trung Duong. Quantum Physics-Informed Neural Network: A Surrogate Model for High-Order ∆-Σ Modulators | 8374 Chia-Wei Liao, Han-Hsuan Lai, Meng-Xun Cai, Wen-Kai Kao, Cheng-Shiun Shen, Yu-Chia Pai, Hou-Xian Ding, Yu-Min Hsu, Richard Kuo, Cheng-Kuo Lin, Wen-Jay Lee, Nan-Yow Chen, Yeong-Her Wang, Yu-Chi Chang and Darsen D. Lu. Deep Learning Assisted Compact Modeling of DC and High Frequency Scattering Parameters for High-Electron Mobility Transistors |
| 15:40 | 8115 Yaohui Lu, Shaoping Wang, Shangyu Wang and Jose M. de la Rosa. Physics-Informed Chain-of-Thought Fine-Tuning of Large Language Models for Explainable High-Level Design of Sigma-Delta Modulators | 3694 Takahiro Yanagi. Exact Fringe Capacitance Modeling via Schwarz-Christoffel Mapping: A Kirchhoff Benchmark for Parallel Plates |
| 16:00 | 5382 Santeri Porrasmaa, Veeti Lahtinen, Verneri Hirvonen, Tomi Valkonen, Aleksi Korsman, Altti Heikkinen, Otto Simola, Aleksi Tamminen and Marko Kosunen. Chippenwolf: Fully Programmatic and Open-source Mixed-mode System-on-Chip Implementation Framework | 3987 Danial Bavi and Sourabh Khandelwal. Computationally Efficient Surface-Potential Calculation in GaN HEMTs with Neural Networks |
| 16:20 - 16:50 | AWARDS AND CLOSING CEREMONY | |