SMACD 2025

Abstract: This tutorial session provides a comprehensive overview of modern System-on-Chip (SoC) verification techniques, spanning foundational RTL validation, agile project management for verification workflows, and advanced methodologies tailored to today’s complex integrated circuits. Attendees will gain insights into creating robust test environments, employing both simulation- and formal-based verification, and effectively managing cross-functional teams and evolving requirements. By exploring real-world examples and best practices—including reusable verification platforms and plug-and-play testbeds—participants will leave with strategies to streamline verification cycles, reduce design errors, and optimize overall development efforts in the face of rapidly advancing semiconductor technologies.

Target Audience: Engineers, researchers, and project managers engaged in integrated circuit (IC) design and verification who are looking to enhance their verification strategies, adopt agile methodologies, and streamline SoC verification for modern complex designs.

Organizer/Company: Electra-IC
Date & Time: (TBD, 90 minutes)
Location: (TBD)

Talk 1: Introduction to Verification
Presenter: Melike ATAY KARABALKAN (Engineering Manager, Electra-IC, İstanbul Türkiye)

SoC Verification ensures that developed integrated circuits meet all specified requirements and function correctly under various conditions. RTL Verification validates the register transfer level code often written in VHDL, Verilog, or SystemVerilog—to confirm design correctness and catch potential bugs early. A typical verification flow includes building robust testbenches, running simulations (using tools like Vivado Simulator, ModelSim, VCS, or QuestaSim), measuring code coverage, and performing both functional and formal verification. Techniques such as assertion-based verification further help detect interface or behavioral issues early in the design cycle.

Talk 2:Your Gateway to Faster, Smarter SoC Verification with Agile Project Management
Presenter: Melike ATAY KARABALKAN (Engineering Manager, Electra-IC, İstanbul Türkiye)
 
Modern SoCs integrate many subsystems—CPUs, GPUs, Ethernet, PCIe, application-specific blocks demanding thorough, efficient, and adaptable verification. With hundreds of tests, frequent bug reports, and rapidly evolving requirements, project management plays a critical role in ensuring timely completion and quality. Agile development principles, originating in software, are increasingly adopted in hardware verification to enable rapid adaptation, better cross-team collaboration, and higher-quality outcomes.

Talk 3: Simplifying Complex SoC Verification for Modern Engineers
Presenter: Merve EYUBOĞLU (Digital Design & Verification Engineer, Electra-IC, İstanbul Türkiye)

The ever-growing transistor counts, and complex functionality make functional verification one of the most resource-intensive phases of chip design. To address this challenge, engineers employ static, dynamic, and formal verification, plus advanced coverage metrics and verification IP (VIP). These methods, combined with reusable frameworks (UVM, UVVM), significantly reduce effort and timelines. However, SoC-level designs add another layer of complexity, requiring combined hardware/software verification, specialized processor verification strategies, and integrated testing of peripheral interfaces or accelerators. A “plug-and-play” SoC testbed capable of verifying the processor core and its surrounding IP/accelerators helps modern teams meet tight schedules and budgets.

Short Biographies

Melike ATAY KARABALKAN
Melike Atay Karabalkan received her BSc in Electronics and Communications Engineering from Yıldız Technical University and her MSc in Electronics and Communications Engineering from Istanbul Technical University. During her graduate studies, she focused on image processing and digital design. She is currently an Engineering Manager at ElectraIC, working on digital design, modeling, and advanced verification for multi-site, high-technology R&D projects. Her experience includes developing digital signal processing designs in VHDL and Verilog, creating MATLAB models, and scripting automated verification flows with TCL. Prior to joining ElectraIC, she developed VHDL-based IP libraries at Koc Information and Defense Technologies and spent four years at TUBITAK (The Scientific and Technological Research Council of Turkey) designing ELINT and COMINT Systems. She has participated in several conferences and authored eight scientific publications.

Merve EYUBOĞLU
Merve Eyuboglu received her BSc in Electronics and Communication Engineering from Istanbul Technical University in July 2024. After completing ElectraIC’s EIC Academy program, she joined ElectraIC as a Digital Design and Verification Engineer. Her interests include digital design, verification, artificial intelligence, and software development. During her undergraduate studies, she worked on a programmable timer module using MicroBlaze on FPGA to control AC servo motors in PLC systems, employing Verilog, C, and MATLAB. She also gained hands-on experience through internships in AI and digital design. Currently, she focuses on RISC-V based SoC verification at ElectraIC.

Tutorial 2
RISC-V & Formal Verification – Emerging Approaches and Practical Insights

Abstract: This tutorial session delves into cutting-edge verification methodologies for modern SoC and processor designs, focusing on the open-source RISC-V architecture and the rising prominence of formal verification. Attendees will discover how flexible, yet increasingly complex RISC-V architectures demand advanced verification frameworks, such as constrained random testbenches and Universal Verification Methodology (UVM), to ensure high coverage and uncover latent design issues. In parallel, the session examines formal verification’s ability to exhaustively explore design state spaces, uncover corner-case defects more efficiently than traditional simulations, and provide mathematical guarantees of correctness. By uniting these themes, the tutorials illustrate how next-generation verification approaches can meet the mounting challenges of today’s heterogeneous, high-performance systems.

Target Audience :This tutorial is ideal for verification engineers, SoC architects, researchers, and technical professionals who want to stay at the forefront of RISC-V verification and learn how formal verification can complement or enhance traditional simulation-based methodologies. Attendees will gain practical insights into emerging techniques, tools, and best practices in verifying complex processor and SoC designs.

Organizer/Company: ANKASYS
Date & Time: (TBD, 90 minutes)
Location: (TBD)



Talk 1: RISC-V Verification: Recent Approaches in Chip Design Verification
Presenter: Elif Betül Şen Özen (ANKASYS, Istanbul, Türkiye)

Processors power virtually every modern device, from consumer electronics to high-end embedded systems. As processor architectures become more intricate to deliver greater performance and specialized functionality, the potential for design errors escalates—making verification a pivotal stage in their development. The RISC-V architecture stands out for its simplicity, modularity, and adaptability, which allows custom instruction extensions for specialized solutions across diverse sectors. However, this very flexibility poses unique verification challenges. In this presentation, we will explore advanced verification techniques tailored for RISC-V, including constrained random verification frameworks like RISCV-DV. These frameworks enable systematic test generation, boosting design coverage and revealing hidden defects. Further, we will discuss how simulation-based approaches—coupled with Universal Verification Methodology (UVM)—provide powerful ways to handle the complex interplay among multiple processor components. Finally, attendees will learn how formal verification can serve as a mathematically rigorous companion to simulation-based testing. By examining emerging trends and future design requirements, this talk highlights the evolving landscape of processor verification.

Talk 2: Formal Verification: An Introduction and Challenges in Practice
Presenter: Yusuf Eren (ANKASYS, İstanbul, Türkiye)

Formal verification is quickly gaining ground as a potent alternative—or complement—to simulation-based methods. As the complexity of modern chip designs continues to rise, purely simulation-driven verification strategies face significant time and coverage challenges. Formal verification, on the other hand, explores the entire state space without having to simulate each scenario, offering significant time savings and the potential to uncover design bugs rapidly—sometimes “over a coffee break.” This presentation delves into the core principles of formal verification, explaining how SAT (Boolean Satisfiability) and SMT (Satisfiability Modulo Theories) solvers work in conjunction with automated formal tools to prove design correctness. Topics will include property-based methods like Bounded Model Checking (BMC) and Prove, as well as strategies to tackle complexity barriers such as abstraction and cut-points. Attendees will learn how these mathematical approaches yield cleaner tape-outs and more reliable systems compared to conventional methods, while understanding the inherent challenges and the evolving role of formal verification in next-generation chip design.

Short Biographies

Elif Betül Şen Özen
Elif Betül Şen Özen received her BSc in Electronics Engineering from Istanbul Technical University and her MSc in Electronics Engineering from Gebze Technical University, where she is currently pursuing a PhD in the same field. Her PhD research focuses on hardware security primitives, particularly Physically Unclonable Functions (PUFs). During her MSc, she worked on mathematical modeling of circuits, periodic steady-state analysis, and sensitivity analysis, leveraging tools such as ADOL-C and Trilinos for numerical solutions. Elif is a Design and Verification Engineer at ANKASYS, where she specializes in advanced verification methodologies, including constrained random testing, error injection, and robustness verification, with SystemVerilog and UVM . She also has experience in VIP development, digital and analog video standards, image processing, signal processing, and numerical analysis. These days, she actively engages in advanced chip design and verification, focusing on RISC-V methodologies and tools, and addressing emerging industry challenges.

Yusuf Eren
Yusuf Eren received his BSc and MSc in Electronics and Electrical Engineering from Harran University, Turkey, where he developed a MIPS/RISC-based custom microcontroller with a custom ISA during his academic studies, showcasing his experience in advanced digital design techniques. After joining ANKASYS as a Design and Verification Engineer, he gained extensive experience in digital design and verification, including work on ASIC and FPGA verification for safety-critical systems, mixed-signal verification, and SoC architecture. In this role, he works on protocols such as PCIe and DisplayPort while focusing on developing Verification IPs, testbenches, and conducting assertion-based testing using UVM. Yusuf is actively engaged in formal verification, applying techniques such as full proof, mutation coverage, bounded model checking, and equivalence checking to ensure design correctness and robustness. He explores state space analysis, utilizes SAT and SMT solvers, and applies advanced abstraction techniques to tackle complex design challenges effectively. Yusuf has authored a paper on SAT/SMT solvers and their applications in formal verification, contributing to industry knowledge and addressing the growing complexities of modern design verification.

Tutorial 3
ML Accelerators on FPGAs – A Journey from Manual Design to AI-Assisted Workflows

Abstract: The growing computational demands of machine learning (ML) have led to the development of specialized hardware accelerators. Field-Programmable Gate Arrays (FPGAs) stand out for their reconfigurability, energy efficiency, and capacity for low-latency processing, making them ideally suited for diverse applications in autonomous systems, healthcare, and data analytics. However, the complexity of FPGA-based ML accelerator design—encompassing hardware-software co-design, resource optimization, and rigorous verification—poses significant challenges, especially under tight development timelines.
This tutorial showcases how AI-assisted workflows, particularly those leveraging Large Language Models (LLMs), can address many of these hurdles by streamlining hardware description language (HDL) generation, error detection, and verification. Through a blend of manual expertise and AI-enabled assistance, designers can reduce debugging time and enhance reliability. Starting with the fundamentals of manual ML accelerator design (including optimization techniques and verification), the session then transitions to in-depth coverage of how LLMs can generate HDL, optimize designs, and improve verification accuracy. Practical demonstrations and real-world case studies illustrate both the promises and limitations of integrating AI into FPGA workflows.
Attendees will learn how to effectively combine traditional and AI-assisted design and verification methods, ultimately crafting scalable hardware solutions that meet modern ML workload demands. This tutorial is particularly relevant for hardware designers, researchers, and industry practitioners seeking to accelerate development cycles and improve design outcomes in next-generation FPGA-based ML systems.
Target Audience: This tutorial is designed for hardware designers, researchers, and industry practitioners looking to innovate in FPGA-based ML accelerator development. Attendees with interests in hardware/software co-design, AI-driven development flows, and optimization strategies will gain valuable insights into both manual and AI-assisted workflows that can significantly enhance efficiency, reliability, and scalability in modern ML acceleration projects.
 
Organizer: Rashed Al Amin, PhD (University of Siegen, Germany)
Date & Time: TBD, 90 minutes
Location: TBD


Session Plan:

Introduction and Motivation
– Overview of FPGAs in ML acceleration.
– Challenges in traditional FPGA workflows.
– Role of LLMs in transforming design and verification.
Fundamentals of ML Accelerator Design
– Key architectural components of ML accelerators on FPGAs.
– Accelerator design and verification Methodologies
– Manual design process and challenges.
Advanced Design Techniques
– Optimization strategies for resource utilization and performance.  
– Case study: Implementation of a Convolutional Neural Network (CNN) on an FPGA.  
– Manual design and verification strategies: simulation and debugging.
AI-Assisted Design and Verification
– Introduction to LLMs in FPGA workflows.
– Demonstration: LLM-aided HDL generation and verification.
– Comparative analysis: Manual vs. AI-assisted workflows.
Q&A and Open Discussion

Short Biography
Rashed Al Amin, PhD
Rashed Al Amin received his B.Sc. degree in Electrical and Electronics Engineering from the University of Dhaka, Bangladesh, and his M.Sc. degree (with the Dean’s Award) in Mechatronics from the University of Siegen, Germany. He completed his PhD in Computer Science at the University of Siegen, where he currently serves as a Scientific Associate and Lecturer at the Chair of Embedded Systems. His research focuses on hardware for artificial intelligence, reconfigurable computing, and FPGA architecture—with a specific goal of designing next-generation FPGAs optimized for deep learning workloads.