Machine Learning for Design Automation

The widespread usage of machine learning and deep learning has fundamentally reshaped the information infrastructure and human society. It also brings new opportunities for design automation of VLSI. With machine learning techniques, labor intensive and time-consuming IC design cycles can be accelerated effectively. This tutorial will present recent research progress on machine learning for various stage in design automation, especially on high level synthesis, timing analysis, thermal modeling and yield analysis.

Tutorial organizer:  Prof. Yuanqing Cheng, Beihang University, Beijing, China.

Participants: Prof. Wei W. Xing, Sheffield University, Sheffield, UK.
 Prof. Kang Zhao, Beijing University of Telecommunications, Beijing China

Talk 1: Heuristic Method for High-level Synthesis

With the increasing speed of chip design iteration, high-level synthesis (HLS) technology is considered an effective shortcut to achieve agile design and development. HLS mainly automatically converts C/C++high-level descriptions into appropriate hardware RTL descriptions, and performs prototype verification on FPGA. The report will introduce high-level integrated processes and key compilation scheduling techniques. From the perspective of the academic community, analyze the difficulties and challenges which can be solved using heuristic algorithms.

Dr. Kang Zhao is the professor of the Beijing University of Posts and Telecommunications (BUPT). He has been deeply involved in the field of integrated circuit EDA for nearly 20 years, and has both college work experience and rich experience in high-end product design of international leading enterprises. In 2009, he got the doctoral degree from Tsinghua University, and then continued to work in Tsinghua for 2 years. Then he worked in Intel, Xilinx and AMD for 12 years. In 2022, he came back to academic. The research focus is mainly on the EDA and FPGA, especially high-level synthesis. When Kang was in Xilinx, he played as a very important role and lead the HLS product team. Except for HLS, he also focused on AIE acceleration, heterogeneous computing, placement and routing.

Talk 2: Machine Learning for Thermal Modeling and Timing

As the integration density on-chip increases quickly with technology node shrinking, thermal dissipation becomes a severe problem for high performance chip design. Although traditional analytical models can capture on-chip thermal profile accurately, they are usually very time-consuming, and difficult to be integrated with iterative physical design phase. So in the first part of this talk, I will introduce recent research progress on using machine learning for thermal modeling such that the thermal aware physical design can be effectively accelerated and the hotspot can be captured as early as possible to mitigate thermal issues before sign-off stage. In addition, today’s billion scale chip design makes timing closure a challenging task due to sharply increase of process corners. In the second part of this talk, I will present how to take advantage of machine learning to accelerate timing analysis for deep sub-micron VLSI design.

Yuanqing Cheng (S 11, M 13, SM 21) received the Ph.D. degree from Institute of Computing Technology, Chinese Academy of Sciences, Beijing, China, in 2012. During 2012 2013, he worked as a post doc researcher in LIRMM, CNRS, France. He is now a tenured associate professor of Beihang University, Beijing. His research interests include reliable and physical design for 3 D integrated circuits, reliable, and low power design for emerging technologies, such as spintronics and carbon nanotube technologies. He has pu b lished more than 50 peer review papers including Proc. of the IEEE, DAC , ICCAD, TVLSI, TCAD, etc. He is an IEEE senior member and the secretary of IEEE CEDA Beijing Chapter.

Talk 3: AI Powered Sampling Methods for Yield Analysis and Optimization

Yield estimation and optimization are two fundamental problems in back end electronic design automation (EDA), particular with the latest technology nodes. In this tutorial, we will introduce how the latest AI method can boost up the yield analysis and optimization with significant speedup and accuracy improvement. From the perspective of the academic community, outline the difficulties and challenges which can be solved using modern AI methods.

Dr. Xing Wei is a lecturer at the University of Sheffield, UK. He earned his Doctorate in the University of Warwick, UK, in March 2017. Dr. Xing specializes in intelligent manufacturing and the industrial application of artificial intelligence, with a notable focus on Electronic Design Automation (EDA). Throughout his career, Dr. Wei has published an impressive array of 50 academic papers in prestigious journals such as Appl. Math. Model. and J. Comput. Phys. He has also made significant contributions to top tier conferences in the realms of artificial intelligence (AAAI, NeurIPS, IJCAI) and EDA (DAC, ICCAD). Dr. Xing’s achievements in yield optimization were highlighted by his nomination for the Best Paper at ICCAD 2023. Additionally, his work in medical image processing was recognized with the Best Academic Poster Award at the IPMI 2019 conference. His research in digital twins won the Beijing Science and Technology Progress Award in 2023.



Exploring Radiation Effects for Reconfigurable SoCs
in Space and Particle Accelerators

The tutorial provides an in-depth overview of electronic failures induced by radiation in radioactive environments, such as space and particle accelerators. The first part delves into the radiation effects, considering the radiation environment of the Large Hadron Collider (LHC) at CERN, emphasizing comparisons with atmospheric conditions. The second part focuses on the reliability analysis of Reconfigurable Systems-on-Chip, discussing challenges and methodologies for evaluating radiation-induced effects on these systems.

Organizers:  Corrado De Sio, Politecnico di Torino
   Matteo Cecchetto, CERN
   Rubén García Alía, CERN

Talk 1: Electronic Failures in the Accelerator Radiation Environment and Test Facilities

The talk introduces the radiation-induced effects in electronics, with a particular focus on the radiation environment in the Large Hadron Collider (LHC) accelerator at CERN, presenting several comparisons with the atmospheric environment. It shows how the radiation levels are measured and simulated in critical areas of the accelerator, focusing on thermal and higher energy neutrons, which are one of the main threats for SEEs. Indeed, SEEs induced by thermal, and 0.01-10 MeV neutrons can induce more failures than high energy neutrons in several locations of the accelerator, and the related Radiation hardness Assurance (RHA) implications are presented. Finally, an overview of the test facilities employed at CERN to measure and qualify electronics is outlined.

MATTEO CECCHETTO received a master’s degree in electronic engineering from the University of Padova (Italy) in 2017 and performed a PhD at CERN (Switzerland), obtaining the degree from the University of Montpellier (France) in 2021. He is currently working on the Radiation to Electronics (R2E) project at CERN. His main activities focus on the experimental and Monte Carlo simulation study of neutron-induced single-event effects in accelerator and fusion environments, with a focus on the effects of thermal and intermediate-energy neutrons and related implications on the qualification approach for electronics.

Talk 2: Reliability Analysis for Reconfigurable Systems-on-Chip

Thanks to their performance, reduced power consumption, and adaptability, Reconfigurable Systems-on-Chip has emerged as a cutting-edge platform for many performance-oriented applications. Additional efforts are needed to ensure the correct system functionality for applications where reliability is a primary concern. Radiation environments are particularly challenging due to the high sensitivity of SRAM-based reconfigurable systems to single-event effects. The tutorial focuses on motivation, challenges, and methodology for evaluating radiation-induced effects on Reconfigurable Systems-on-Chip.

CORRADO DE SIO received the M.S. degrees in Computer Engineering from the University of Pisa, Pisa, Italy, in 2018. He received his Ph.D. from Politecnico di Torino, Turin, Italy, in 2023. Currently, He is working in the CAD & Reliability group of the Department of Computer and Control Engineering of Politecnico di Torino as a Postdoctoral Research Assistant and member of the Aerospace, Safety and Computing (ASaC) Lab. His research interests include reconfigurable devices, radiation effects, and EDA tools for analyzing and improving the reliability and the design of embedded and reconfigurable systems applications.